The present invention relates to a multi-chip module including a plurality of semiconductor chips, and to a configuration of a semiconductor chip incorporated in a multi-chip.
In recent years, a concept of one-chip system LSI has been proposed in which a plurality of functions are incorporated in a single chip, and various proposals have been made as to design methods for one-ship system LSIs. Particularly, an advantage of a one-chip system LSI is in that a high-performance and multi-function device can be realized by integrating, in a single semiconductor chip, various functions including memories such as DRAMs and SRAMs, logic circuits, and analog circuits. However, the realization of such a system LSI, i.e., the manufacture of a device incorporating a plurality of functions therein has confronted the following problems.
The first problem is that a greater development power is required to increase the scale of a system LSI, and an increase in the chip area decreases the manufacturing yield, thereby increasing the device manufacturing cost.
The second problem is that a process for mixing different types of devices such as a DRAM and a FLASH is difficult to adjust to match a pure CMOS process, whereby when developing a process for a device for realizing a function, it is very difficult to start up the development at the same time with a pure CMOS process. Therefore, the development of the process for mixing different types of devices is delayed by one or two years from that of a state-of-the-art pure CMOS process, thereby failing to make a timely manufacture/supply to meet the needs of the market.
With regard to these problems, a chip-on-chip type system LSI has been proposed which is obtained by making a plurality of chips into a module, as disclosed in Japanese Laid-Open Patent Publication No. 58-92230. The chip-on-chip type multi-chip module technique is a technique of connecting, via bumps, pad electrodes provided on the upper surface of a chip to be a substrate (a parent chip) with pad electrodes provided on the upper surface of a chip to be mounted (a child chip), and attaching the chips to each other for electrical connection between the chips, thereby making the plurality of chips into a module. With the chip-on-chip type multi-chip module technique, as compared with a one-chip system LSI, a plurality of functions are incorporated in a plurality of chips in a dispersed manner, whereby it is possible to reduce the scale of each chip and to improve the yield of each chip. Furthermore, different types of devices of different process generations can be easily made into a module, whereby it is easy to increase the functionality. Moreover, in a system LSI using the chip-on-chip type multi-chip module technique, as compared with other multi-module techniques, the wire length required for the interface between the parent and child chips is very small, whereby it is possible to realize a high-speed interface, and to realize a performance as that of a block-to-block interface in a conventional one-chip system LSI.
As described above, the chip-on-chip type multi-chip module technique is an important technique replacing the conventional one-chip system LSI, but has the following problems.
Typically, in a bare-chip IP using a minute process, the operating voltage of an internal circuit is different from the voltage of an interface circuit between the bare-chip IP and an external device. Therefore, in order to form a multi-chip module, there is required a process for forming a plurality of types of transistors whose gate insulating films have different thicknesses.
Moreover, in a case where a plurality of bare-chip IPs are made into a multi-chip module, and where an interface with an external device outside the multi-chip module is required for each bare-chip IP, it is necessary to provide, for each bare-chip IP, at least two different transistors having different withstand voltages, i.e., one having a withstand voltage for an interface circuit and the other having a withstand voltage for an internal circuit. Thus, when manufacturing each bare-chip IP, there is required a process for forming transistors having a plurality of types of gate insulating films of different thicknesses.
As a result, it is not possible to avoid an increase in the process cost.
Moreover, in a case where the bare-chip IPs are used for general purposes, it is necessary to take into consideration that an input/output terminal of each bare-chip IP is to be connected to an external device outside the multi-chip module, whereby it is necessary to provide a surge protection function in all input/output circuits of each bare-chip IP.
An object of the present invention is to provide a configuration of a multi-chip module that can be manufactured at a low cost and a semiconductor chip suitable therefor, by simplifying a process for manufacturing a semiconductor chip to be a bare-chip IP to be incorporated in a multi-chip module.
A semiconductor chip of the present invention is an I/O semiconductor chip provided in a multi-chip module that includes a plurality of semiconductor chips and a plurality of external terminals, the I/O semiconductor chip including an input/output function section including a plurality of input/output circuits that are provided between the plurality of semiconductor chips and the plurality of external terminals.
In this way, all the interfacing between the semiconductor chips in the multi-chip module and the external devices outside the multi-chip module is provided through the input/output function section of the I/O semiconductor chip. Therefore, when configuring the multi-chip module, it is not necessary to provide a transistor that operates with a voltage for the interface circuit, in the semiconductor chips other than the I/O semiconductor chip. As a result, when manufacturing the semiconductor chips, it is possible to reduce the number of types of transistors, e.g., it is possible to form only one type of transistors having the same thickness, whereby the manufacturing process is simplified and the manufacturing cost can be reduced.
Moreover, since the semiconductor chips other than the I/O semiconductor chip have no interface with external devices, it is possible to eliminate the need for a surge protection member in each semiconductor chip or to reduce the function of the surge protection member. Thus, it is possible to reduce the area of each semiconductor chip.
On the other hand, the capacitance incurred by the surge protection circuit that is necessary for the interface between the semiconductor chips in the multi-chip module is very small as compared with that in the prior art. Therefore, it is possible to increase the speed of the interface in the multi-chip module, and to reduce the power consumption of the multi-chip module.
Moreover, even when there are various interfaces with various specifications between the semiconductor chips in the multi-chip module and the external devices outside the multi-chip module, it can be addressed flexibly by appropriately setting the function of the I/O semiconductor chip without changing the functions of the other semiconductor chips.
Even changes of the I/O specifications can be addressed flexibly by appropriately setting the configuration of the input/output section of the I/O semiconductor chip without changing the functions of the other semiconductor chips.
It is preferred that: the plurality of external terminals include a power supply terminal and a ground terminal; and the input/output function section includes a power supply section connected to the power supply terminal for supplying a power supply voltage to the plurality of semiconductor chips, and a ground voltage supply section connected to the power supply terminal for supplying a ground voltage to the plurality of semiconductor chips.
If a surge protection member provided between the ground terminal among the plurality of external terminals and one or more of the plurality of external terminals excluding the ground terminal is further included, it is possible to, when configuring the multi-chip module, eliminate the need for a surge protection member in each semiconductor chip other than the I/O semiconductor chip or to reduce the function of the surge protection member.
It is preferred that the plurality of input/output circuits of the input/output function section are configured so as to be able to individually select a power supply voltage.
At least one of the plurality of input/output circuits of the input/output function section may be configured so as to be switchable between an input function of receiving a signal from the semiconductor chip that is connected to the input/output circuit and an output function of outputting a signal to the external terminal to which the input/output circuit is connected.
If the input/output circuits receive a plurality of power supply voltages and include a level shift circuit for converting a voltage level from a level of a first voltage among the plurality of power supply voltages to a level of a second voltage, it is possible to ensure an input/output function even when the operating voltage of the internal circuit of the semiconductor chip is different from that of the external device.
In this case, it is preferred that the first voltage and the second voltage are configured so that a voltage value can be selected for each of the input/output circuits in the input/output function section.
A first multi-chip module of the present invention includes a plurality of semiconductor chips and a plurality of external terminals, the multi-chip module including an I/O semiconductor chip that includes an input/output function section including a plurality of input/output circuits provided between the plurality of semiconductor chips and the plurality of external terminals.
In this way, it is possible to realize the basic effects of the semiconductor chips in a multi-chip module.
A second multi-chip module of the present invention includes a group of small chips mounted on a large chip that includes a plurality of external terminals, the multi-chip module including an I/O semiconductor chip that includes an input/output function section including a plurality of input/output circuits provided between the plurality of external terminals on the large chip and individual ones of the group of small chips.
It is preferred that the large chip is a substrate dedicated for wiring that does not include a semiconductor element.
In this way, the manufacturing process for a semiconductor chip to be a substrate on which small chips are mounted can be simplified, whereby the manufacturing cost can be reduced and the developing time can be reduced. Furthermore, by employing a dedicated wiring substrate, it is possible to avoid disadvantages due to miniaturization of wiring, such as deterioration of the power supply impedance and an increase in the wiring delay. Moreover, since the semiconductor chip to be a substrate does not have a semiconductor element such as a transistor, a yield of substantially 100% can be expected, and the pre-shipping test of the substrate chip can be simplified in some cases, thereby further reducing the cost. Moreover, since there are no semiconductor elements on the semiconductor chip to be a substrate, the semiconductor chip can be designed so as to ensure only an area that is required for making the module, thereby considerably increasing the freedom in the selection and design of the small chips to be mounted thereon. Moreover, since the semiconductor chip is a dedicated wiring substrate, a minute pattern is not needed, whereby the existing semiconductor processes of old generations can be reused, and it is possible to provide a substrate chip at a lower cost.